Comparative Energy and Delay of Energy Recovery and Square Wave Clock Flip-Flops for High-Performance and Low-Power Applications

Flip-flops are essential elements of a design from both delay and energy aspects. A significant fraction of the total power in highly synchronous systems 1s dissipated over clock networks. Hence, lowpower clocking schemes are promising approaches for future desfgns. Recently, there has been published several energy recovery flip-flops that enable energy recovery from the clock network, resulting in significant energy savings. However, there has not been shown any extensive power and delay comparison between energy-recovery and square clock flip-flops. We compare the energy recovery flip-flops with square wave clock flip-flops in terms of power, delay, and area. Based on the simulation results using BPTM 0.18pm CMOS technology, at a frequency of 2OOMH2, the differential energy recovery flip-flops exhibit more than 14% delay reduction and power reduction of more than 4% compared to the differential squarewave clock flip-flops. The singie-ended energy recovery flip-flops show more than 22% delay reduction and power reduction of more than 16% compared to the slngie-endcd square wave clock flip-flops.